Delay Fault Test Generation for Circuits with Standard Scan Design Considering Three-State Elements EXTENDED PRESENTATION ABSTRACT
نویسندگان
چکیده
Short Abstract Most industrial digital circuits contain three-state elements besides pure logic gates. We like to presents a gate delay fault test generator for sequential circuits with standard scan design that can handle three-state elements like bus drivers, transmission gates and pulled busses. The delay test pattern generator is based on a well-proved stuck-at test pattern generator that was combined with an efficient gate delay fault simulator. The fault simulator, featuring a 101-valued logic, is used to evaluate the quality of a generated gate delay test. Experimental results for ISCAS89 benchmark circuits will be presented as well as results for industrial circuits containing three-state elements.
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